Thyristors have been used as indispensable devices for large capacity power conversion due to their low on-voltage characteristics. Specifically, GTO (gate turn-off) thyristors are used very often in the high-voltage large-current range applications. Drawbacks of the GTO thyristors, however, have also become clear. The drawbacks include the fact that the GTO thyristors require a large gate current for turning-off, that is a turn-off gain of the GTO thyristors is small, and the fact that the GTO thyristors require large snubber circuits for their safe turn-off. In addition, since the GTO thyristors do not show current saturation in their current-voltage characteristics, the GTO thyristors require passive components such as a fuse etc. for protecting the load from a short-circuit. This causes a bottle neck against down sizing and cost reduction of the power converting apparatuses.
AMOS control thyristor (MCT), proposed by V. A. K. Temple (IEEE IEDM Tech. Dig., 1984, p282), may be classified into a voltage drive type device. Since then, analysis and improvement of the MCT have been done world wide, since the MCT can be driven with a much simpler gate circuit than the GTO thyristors, and since the MCT turns on at low on-voltage. However, the MCTs also require passive components in their practical use, since the MCT does not show current saturation characteristics too.
M. S. Shekar et al. have experimentally shown that a dual channel type emitter switched thyristor (EST) shows current saturation characteristics up to high voltage range (IEEE Electron Device Letters, Vol. 12 (1991) p387). The inventor of the present invention analyzed the forward bias safe operation area (FBSOA) of the EST (cf. Proceedings of IEEE ISPSD '93, P71, and Proceedings of IEEE ISPSD '94, P195), and has opened up a way for developing a voltage drive type thyristor which operates safely even when a load is short-circuited. FIG. 2 is a partly perspective isometric view of an EST device developed by the present inventor.
In this device shown in FIG. 2, an n.sup.+ buffer layer 2 is deposited on a p.sup.+ emitter layer 1, and an n.sup.- base layer 3 is deposited on the n.sup.+ buffer layer 2. In a surface layer of the n.sup.- layer 3, the first p-base region 4, a p.sup.+ base region 5 which occupies a part of the first p-base region 4, and the second p-base region 6 are formed. An n.sup.+ source region 7 is formed in a surface layer of the first p-base region 4, and an n.sup.+ emitter region 8 is formed in a surface layer of the second p-base region 6. A gate electrode 10 is deposited on a gate oxide film 9 from above a region of the first p-base region 4 sandwiched between the n.sup.+ source region 7 and an exposed area of the n.sup.- base layer 3 to above a region of the second p-base region 6 sandwiched between the n.sup.+ emitter region 8 and the exposed area of the n.sup.- base layer 3. The length of the source region 7, the emitter region 8 and the gate electrode 10 is limited in Z-direction of FIG. 2, and the first p-base region 4 and the second p-base region 6 are connected outside the limited length of the source region 7, the emitter region 8 and the gate electrode 10. Outside the connection of the first p-base region 4 and the emitter region 8, the p.sup.+ base region 5 extends in L-shape. A cathode 11 contacts in common with an L-shape surface of the p.sup.+ base region 5 and n.sup.+ source region 7. In addition, an anode 12 contacts with an entire surface of the p.sup.+ emitter layer 1.
By grounding the cathode 11 of this device, and by applying positive voltage to the gate electrode 10 in a state in which the anode 12 is biassed positive, an inversion layer (partial storage layer) is formed under the gate oxide film 9 and a horizontal MOSFET is turned on. By this operation, electrons are fed from the cathode 11 to the n.sup.- base layer 3 via the n.sup.+ source region 7 and the channel formed in the surface layer of the first p-base region 4. The electrons function as a base current of a PNPN transistor, consisted of the p.sup.+ emitter layer 1, the n.sup.+ buffer layer 2, the n.sup.- base layer 3, the first p-base region 4, the second p-base region 6, and the p.sup.+ base region 5, and drives the PNPN transistor. Holes are injected from the p.sup.+ emitter layer 1, and flow to the second p-base region 6 via the n.sup.+ buffer layer 2 and the n.sup.- base layer 3. Then the holes flow under the n.sup.+ emitter region 8 in Z-direction to the cathode 11. Thus, the device operates in an IGBT mode. As the current further increases, a PN junction between the n.sup.+ emitter region 8 and the second p-base region 6 is forward biased, and a built-in thyristor consisting of the p.sup.+ emitter layer 1, the n.sup.+ buffer layer 2, the n.sup.- base layer 3, the second p-base region 6 and the n.sup.+ emitter region 8, is latched up. In turning off the EST, the MOSFET is switched off by lowering the potential of the gate electrode 10 below the threshold of the horizontal MOSFET. By this operation, the potential of the n.sup.+ emitter region 8 is separated from that of the cathode 11, and the thyristor mode of operation stops.
Since the EST shows current saturation characteristics, the EST can be used for an output stage of power ICs. A horizontal structure which facilitates integrating the ESTs is disclosed in IEEE IEDM Tech. Dig. 1993 by R. Sunkavalli et al. FIG. 3 is an isometric view showing a device structure of the horizontal EST. In FIG. 3, common parts with those of FIG. 2 are designated by the same reference numerals. In FIG. 3, an oxide insulation layer 32 is deposited on an n.sup.+ substrate 31, and an n.sup.- base layer 3 is deposited on the oxide insulation layer 32. In a surface layer of the n.sup.- base layer 3, the first p-base region 4, a p.sup.+ base region 5, the second p-base region 6, an n.sup.+ source region 7, and an n.sup.+ emitter region 8 are formed. In a surface layer on the same side of the n.sup.- base layer 3, the n.sup.+ buffer layer 2 and an p.sup.+ emitter layer 1, with which an anode 12 contacts, are selectively formed.
As suggested by the above explanation, since the PN junction between the second p-base region 6 and the n.sup.+ emitter region 8 is forward biased by the holes flowing in Z-direction of the second p-base region 6, the forward bias lowers in Z-direction as approaching the contact area of the second p-base region 6 with the cathode 11. That is, amount of the electrons injected from the n.sup.+ emitter region 8 is not uniform along Z-direction. When the EST is turned off from such the on-state, the junction recovers its reverse-blocking ability from a shallowly biassed part near the contact area with the cathode 11 and delays recovering in the farthermost part from the cathode contact area. This causes current localization and lowering of the breakdown withstand capability at turning off.
FIGS. 4 and 5 are sectional views showing improved ESTs disclosed in U.S. Pat. Nos. 5,317,171 (May 31, 1994) and 5,319,222 (Jun. 7, 1994) by M. S. Shekar et al. Though the EST of FIG. 4 operates in the same way as the ESTs of FIGS. 2 and 3, a cathode 11 extends in Y-direction and contacts directly with the second p-base region 6. This configuration facilitates quick and simultaneous turning off, since the hole current in Z-direction is not utilized. However, the on-voltage of the device of FIG. 4 does not lower as expected, since minority carriers are not uniformly injected along Y-direction even if the PN junction between the n.sup.+ emitter region 8 and the second p-base region 6 were biassed in forward in the thyristor mode of operation. If the impurity concentration of p-base region is decreased and its resistance is increased to solve the above described problem, sufficient withstand voltage is not obtained, since a depletion layer punches through to the n.sup.+ emitter region 8 when a cathode 11 is negatively biased and an anode 12 is positively biased.
In the device of FIG. 5, though an n.sup.+ emitter region 8 extends from an p-base region 6 for further lowering the on-voltage, this device structure causes insufficient forward withstand voltage.
An IGBT and a thyristor are connected in parallel in the ESTs. The on-voltage lowers with an increasing area of the thyristor. In addition, the on-voltage lowers with an increasing current amplification factor of an NPN transistor of the thyristor.
In view of the foregoing, an object of the present invention is to provide an insulated gate thyristor which facilitates uniformly recovering reverse-blocking ability of the PN junction at turning-off to increase the turn-off withstand capability and lowering the on-voltage.